1. Technical Field
The present invention is directed to a device and a method for converting parallel data to serial data; in particular, a device and a method for converting n-bit parallel data to serial data using n-subfrequency clocks.
2. Discussion of Related Art
In high speed data links where a large amount of data is to be transmitted and received at separate data ports or remote locations, it is customary to convert the data from parallel to serial format by a parallel to serial converter for transmission over a high bandwidth channel such as fiber optics. The transmitted data is received at the other end of the fiber channel in serial format. The received data is converted back to parallel data by a serial to parallel converter for processing at the receiving end. The fiber channel is capable of transferring data at the rate of tens to hundreds of gigabits per second. The limitation of the rate of transfer is often the limited speed of operation of the parallel to serial converter.
A conventional parallel to serial converter is shown in FIG. 1. The parallel to serial converter 100 converts a ten bit parallel data to output as serial data. (As shown, the ten bit parallel data is actually eight bits wide with a xe2x80x981xe2x80x99 bit and a xe2x80x980xe2x80x99 bit boundary.) Ten NAND gates 110 corresponding to the ten data bits of parallel data are output through OR gate 130. Ten subfrequency clocks xcfx860 to xcfx869 are connected to NAND gates 110 to multiplex the ten bits of input data to output the data one at a time through NAND gates 110. The ten subfrequency clocks are derivatives of the system clock, each being equally spaced by a delay of duration about T/10, wherein T is the period of the system clock. Only two of the ten subfrequency clocks are both at logic xe2x80x981xe2x80x99 for a duration of T/10. With the subfrequency clocks conntected to the NAND gates 110 as shown in FIG. 1, the ten bit input data is enabled to pass the NAND gates in order. Ten D flip flop latches 121 are clocked by system CLOCK 1 for holding the 10 BIT data. If the parallel to serial converter of FIG. 1 did not include a second set of flip flop latches 125, there would be insufficient setup time and hold time to allow the proper clocking and conversion of parallel data to serial data. The setup time refers to an interval between a rising transition edge on any of data 0 to 7 and a rising transition edge on a clock for clocking the data into a holding register. The hold time refers to an interval between a falling transition edge on any of data 0 to 7 and a falling transition edge of a corresponding clocking clock signal. In the conventional parallel to serial converter of FIG. 1, the second set of latches 125 receives the second half of data 0 to 7 upon receipt of a second clock signal CLOCK 2, which transitions to clock data 4 to 7 into latch 125 at about the half cycle of CLOCK 1. With the second set of latches 125, the latter half of the 10-bit data is held for an additional T/2 interval. This allows a new set of 10-bit data to be loaded onto latches 121 after the transition of CLOCK 2.
FIG. 2 shows the timing relationshp of data 0-9 being clocked into latches 121 with the low to high transition of CLOCK 1 and data 5-9 being clocked into latches 125 with the low to high transition of CLOCK 2 at about half cycle of clocking period of CLOCK 1. With the second set of latches 125, extra setup time and hold time can be provided. The parallel to serial converter shown in FIG. 1 is further described in U.S. Pat. No. 5,714,904, the disclosure of which is incorporated-by-reference herein. With extra setup and hold time, a parallel to serial converter can operate at higher data rates without error due to insufficient setup and hold times.
Accordingly, a need exists for a parallel to serial converter for converting parallel data to serial data and provide extra setup and hold times and to facilitate reliable operation at high speed.
According to an aspect of the present invention, a circuit is provided for serializing parallel data of N bits, which comprises a first register for storing M bits of the parallel data, M being less than N, the first register being clocked by a first clock; at least one second register other than the first register for storing at least N-M bits of the parallel data, the at least one second register being clocked by at least one second clock which is different in phase from the first clock; at least one third register for storing at least the nth and (nxe2x88x921)th bits of parallel data output from the at least one second register, the third register being clocked by at least one third clock which is different in phase from the first and the second clocks; and logic gates for receiving as inputs the N bits of parallel data output from the first register and output from one or both of the at least one second register and the third register to form N serial data.
The circuit preferably further includes a plurality of n-phased clocks, each having a different phase from the other for coupling to the inputs of the logic gates, wherein the logic gates include N gates corresponding to the N bits of data, wherein the nth bit data is input with the nth phased and ((N/2)+nth+1) phased clocks to the nth logic gate.
Preferably, the duration of time between the first clock and the second clock is substantially one third the period of a clock frame in which each of the n-phased clocks has transitioned once, wherein each of the n-phased clocks transition once within every repeated clock frame, and the first, second, and third clocks transition once within a register clock frame, and the nth bit data is output as serial data after the transition of the third clock in the register clock frame but before the end of the next register clock frame.
According to another embodiment of the invention, the at least one second register comprises two registers and the at least one second clock comprises two clocks having low to high transitions at different times within a clock frame. Alternatively, the at least one-third register comprises two registers clocked by the at least one third clock which comprises two clocks having transitions at different times.
According to a second aspect of the present invention, a circuit for serializing parallel data of N bits is provided, comprising a first register for storing M bits of the parallel data, M being less than N, the first register being clocked by a first clock; a second register for storing P bits of the parallel data, the second register being clocked by a second clock which is different from the first clock; a third register for storing Q bits of the parallel data, wherein M+P+Q=N, the third register being clocked by a third clock; and a fourth register for storing data output from the third register, the forth register being clocked by a forth clock which is different from the first, second, and third clocks; and logic gates for receiving as inputs the N bits of parallel data output from the first, second, and forth registers to form N serial data, wherein the third clock is the same as the first clock.
A method for serializing parallel data of N bits is also provided, comprising the steps of storing M bits of the parallel data in a first register, M being less than N, the first register being clocked by a first clock; storing P bits of the parallel data in a second register, the second register being clocked by a second clock which is different from the first clock; storing Q bits of the parallel data in a third register, wherein M+P+Q=N, the third register being clocked by a third clock; and storing data output from the third register in a fourth register, the fourth register being clocked by a fourth clock which is different from the first, second, and third clocks; and receiving as inputs at logic gates the N bits of parallel data output from the first, second, and forth registers to form N serial data.
An alternative method for serializing parallel data of N bits is also provided, comprising storing M bits of the parallel data in a first register, M being less than N, the first register being clocked by a first clock; storing at least N-M bits of the parallel data in at least one second register other than the first register, the at least one register being clocked by at least one second clock which is different from the first clock; storing at least the nth and (Nxe2x88x921)th bits of parallel data output from the at least one second register in at least one third register, the third register being clocked by at least one third clock which is different from the first and the second clocks; and receiving as inputs at logic gates the N bits of parallel data output from the first register and output from one or both of the at least one and the third registers to form N serial data.